R
Table 1-5:
DIP Switch Connections (SW4) (Continued)
Detailed Description
SW4
GPIO_DIP_SW6
GPIO_DIP_SW7
GPIO_DIP_SW8
FPGA Pin
U5
U7
T7
7. User and Error LEDs (Active-High)
There are a total of 15 active-High LEDs directly controllable by the FPGA:
?
?
?
Eight green LEDs are general purpose LEDs arranged in a row
Five green LEDs are positioned next to the North-East-South-West-Center-oriented
pushbuttons (only the center one is cited in Figure 1-2, page 12 )
Two red LEDs are intended to be used for signaling error conditions, such as bus
errors, but can be used for any other purpose
Some LEDs are buffered through the CPLD to allow the LED signals to be used as higher-
performance I/O by way of the XGI expansion connector. Table 1-6 summarizes the LED
definitions and connections.
Table 1-6:
User and Error LED Connections
ML501 Evaluation Platform
Reference
Designator
DS20
DS21
DS22
DS23
DS24
DS17
DS16
DS15
DS14
DS13
DS12
DS11
DS10
D56
D55
Label/Definition
LED North
LED East
LED South
LED West
LED Center
GPIO LED 0
GPIO LED 1
GPIO LED 2
GPIO LED 3
GPIO LED 4
GPIO LED 5
GPIO LED 6
GPIO LED 7
Error 1
Error 2
Color
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Green
Red
Red
FPGA Pin
Y8
Y18
AA8
AA18
T22
E13
D14
E12
F12
D15
E15
E10
E11
N4
P5
Buffered
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
19
UG226 (v1.4) August 24, 2009
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